1. Field of the Invention
The present invention relates to a shift register circuit, and more particularly, to a shift register circuit capable of reducing a period required for pulling down a gate signal.
2. Description of the Prior Art
Liquid crystal displays (LCDs) have advantages of a thin profile, low power consumption, and low radiation, and are broadly adopted for application in media players, mobile phones, personal digital assistants (PDAs), computer displays, and flat screen televisions. The operation of a liquid crystal display is featured by modulating the voltage drop across opposite sides of a liquid crystal layer for twisting the angles of liquid crystal molecules in the liquid crystal layer so that the transmittance of the liquid crystal layer can be controlled for illustrating images with the aid of light source provided by a backlight module. In general, the liquid crystal display comprises plural pixel units, a source driver, and a shift register circuit. The source driver is utilized for providing plural data signals to be written into the pixel units. The shift register circuit comprises a plurality of shift register stages and functions to generate plural gate signals for controlling the operations of writing the data signals into the pixel units. That is, the shift register circuit is a crucial device for providing a control of writing the data signals into the pixel units.
However, in the operation of a prior-art shift register circuit, each gate signal provided by one corresponding shift register stage cannot be quickly pulled down from high level voltage to low level voltage following the level switching of system clock, thereby reducing the effective charging time of pixel unit. That is, the charging rate of pixel unit is hard to boost. In some prior-art shift register circuits, the size of driving transistor in each shift register stage is enlarged for enhancing pixel charging rate, which results in significantly higher power consumption. Besides, if the shift register circuit is integrated in a display panel comprising pixel array to bring the cost down, i.e. based on a gate-driver on array (GOA) architecture, the aforementioned shift register stages are sequentially arranged in a lengthy border area of the display panel so that each shift register stage can be directly connected to one corresponding gate line, and dimensions of the lengthy border area are required to increase for housing driving transistors with increased size.